Microelectronic devices such as IC (integrated circuit) packages can include multiple layers of stacked semiconductor die (“die”) vertically placed on top of one another, with the stacked die, in many examples, supported on a package substrate. In conventional stacked die configurations, the multiple die will typically be stacked directly on top of one another. In some cases, the die may be stacked in terms of decreasing dimensions, so that each higher die fits within the available area of the die below. In other conventional packages multiple essentially identical die may be stacked directly on top of one another; and in some cases can be interconnected through silicon vias (“TSVs”), to communicate with a supporting substrate below. In these types of packages, where the size and configuration of the die used in the package is limited by the stacking constraints, that limitation provides a barrier to integration of different die types and sizes into the IC package.
A common problem with such stacked die IC packages is that conventional die stacking provides limited capability for thermal dissipation, leading to heat accumulation and/or entrapment within the package. Such heating can lead to premature failure, or degradation of reliability of one or more of the die within the package due to e.g. increased device junction temperature (Ti). This becomes a particular problem as many packages seek to combine multiple “ultra-thin” die (e.g., die having a thickness at or less than 100 μm), in a package. Some such “ultra-thin” die may have a thickness ranging 20 μm to 100 μm. Additionally, many packages seek to combine devices of different types, such as, for example, processors, memory (such as, for example, flash memory or dynamic random-access (“DRAM”) memory), radio frequency (“RF”) devices, and other types of analog, digital, and/or mixed-signal devices. In various embodiments such combined devices will often have different degrees of heat sensitivity (in terms of failure or degradation) and heat generation. Additionally, some types of devices, for example processors, may have regions that are particularly thermally-active-regions in which substantially greater heat is generated than in other regions of the device.
Conventional attempts to mitigate the described heating problems include thermal interface materials, thermally conductive encapsulant for the package (to assist in transferring heat out of the package), and various forms of heat spreading structures. These thermal management materials can add cost to the package, and can often be of less than optimal utility in their ability to transfer heat trapped between stacked ICs.
As a result, it would be beneficial to provide a structure for stacked die microelectronic device packages that would facilitate greater flexibility in integration of multiple die into the stacked package, and/or that would better facilitate dissipation of heat generated by one or more of the stacked die in the package.